Keynotes on April 7th, 2025
Forward-Looking Roadmap: Enabling Heterogeneous Integration in the Next Decade
Gamal Refai-Ahmed, Ph.D., PEng, FIEEE, LFASME, FEIC
AMD, US
Abstract
Coming soon

Gamal Refai-Ahmed, Ph.D., PEng, FIEEE, LFASME, FEIC
AMD, US
Multi-Physics Simulations: Accelerating Microelectronics Packaging for Artificial Intelligence Applications
Mudasir Ahmad
Google, US
Abstract
Coming soon

Mudasir Ahmad
Google, US
Failure Analysis Beyond Moore’s Law: Challenges and a Roadmap Forward
Lesly Endrinal
Google
Lesly Endrinal is the Silicon Failure Analysis Technical Lead responsible for building the first Silicon Electrical Fault Isolation (EFI) lab in Google. Prior to Google, she was a Principal Engineer from Qualcomm Technologies Inc, responsible for driving Design for Test and Failure Analysis strategies to enable yield bring up and design debug. Lesly has 25 years of combined experience in Failure Analysis, Reliability, Product and Test Engineering. She currently chairs the Electron Device Failure Analysis Society (EDFAS) Die Level Roadmap Council and owns 9 patents on Design for FA and DFT across the globe. She is an author of several papers, two of which won Best Paper awards at the International Symposium for Testing and Failure Analysis conference.
Abstract
The fast-paced evolution of technology, driven by innovations such as 5G, artificial intelligence, augmented reality and quantum computing, has fueled a growing demand for high-performance integrated circuits (ICs). This demand requires integrated circuits (ICs) to operate at higher speeds and with reduced power consumption. Transistor scaling consistently followed Moore’s Law for decades, but in the recent years, we have witnessed a slowdown as we achieve the physical limits of manufacturing silicon transistors. In spite of these obstacles, the process technology still managed to keep up, but the steady increase in transistor density has resulted in escalating lithography costs and complexities, leading to significant yield losses that hurt the product. To mitigate these challenges and achieve optimal performance, power, area, and cost (PPAC), design technology co-optimization (DTCO) and system technology co-optimization (STCO) initiatives have been adopted. However, despite advancements in PPAC optimization, the continuous scaling of transistors, coupled with the growing complexity of logic design, lower power consumption and increasingly complex 3D IC package schemes, introduces new obstacles for failure analysis. Current and future package technologies incorporate multiple layers of various components stacked on top of one another with decreasing bump pitch, projected to reach sub-micron dimensions. This complex package design makes it difficult to inspect and access specific components or interconnects of interest while keeping the device still intact.
This presentation will delve into the Failure Analysis challenges highlighted by a comprehensive study conducted by over 50 experts from more than 30 leading organizations across industry, academia, national labs, and research institutes, facilitated by the Electron Devices Failure Analysis Society (EDFAS) through its Technology Roadmap initiative. As chair of the Die Level Isolation Roadmap committee, I will present the key Electrical Fault Isolation (EFI) challenges, identify critical gaps, and outline indicators for success. This covers five critical areas of focus: (1) laser-based, photon emission, and thermal techniques; (2) 2D/2.5D/3D packaging; (3) product yield, test, and diagnostics; (4) leading edge technologies; and (5) system level, analog/RF, and digital functional analysis. Furthermore, this presentation will highlight the key challenges associated with post-isolation and physical failure analysis, encompassing sample preparation, nano-probing/scanning probe microscopy, Scanning Electron Microscopy (SEM), and Focused Ion Beam (FIB) microscopy. Furthermore, this presentation will provide a brief overview of key package-level failure analysis (FA) bottlenecks. Finally, it will explore opportunities for collaboration between the simulation community and failure analysis experts to improve the quality and success of failure analysis.

Lesly Endrinal
Google
Connected Outdoor Lighting: from Big Data to Reliability Predictions
Piet Watte & Ger van Hees
Signyfy, the Netherlands
Abstract
Coming soon

Piet Watte & Ger van Hees
Signyfy, the Netherlands