Keynotes on April 7th, 2025

This talk will examine the transformative advancements and challenges shaping the future of heterogeneous integration (HI) over the next ten years. By exploring both prior innovations and state-of-the-art technologies, the presentation will highlight key issues in semiconductor manufacturing, thermal management, and advanced packaging. With a focus on current industry challenges such as global chip shortages and strategic initiatives like the US CHIP Act, the talk will emphasize the need for robust technological roadmaps to support AI, HPC, and other next-generation applications.

A central theme will be the future of heterogeneous integration through chiplet technology, which holds the promise of revolutionary advancements but faces significant challenges. The discussion will delve into the critical trade-offs related to package substrates, silicon die size, power density, thermal resistance, package coplanarity and warpage, and ball-grid array assembly. Addressing these factors is essential for developing thermal and mechanical solutions that support ongoing technological progress.

Looking forward to 2033, the shift toward larger die sizes may necessitate the adoption of a System on Wafer (SoW) approach to overcome the constraints posed by chiplet-based integration. Achieving this vision will require a strong collaboration between industry and academia to drive advancements in heterogeneous integration, unlocking the full potential of this critical technology.

The Global Artificial Intelligence (AI) market was valued at USD 150 billion in 2023 and is projected to grow at a CAGR of 36.8% to reach USD 1,345 billion by 2030. From computer vision to natural language processing to co-pilots, AI applications are rapidly expanding and are permeating virtually every aspect of business and personal life. Key to the growth of AI are the plethora of software and hardware that process large amounts of data for training and inference. 

Advanced Packaging has been enabling other applications like High Performance Computing, Networking, IoT etc., which in turn are driving AI growth. In addition, AI applications such as AI Accelerators require specialized hardware to enable the speed, cost, scaling, and reliability needed for deploying AI on the scale and complexity expected over the next decade. 

While the pace of AI development is so fast, advanced packaging is becoming more expensive with much longer development times. A foundational technology to help bridge this gap between rapid AI development and advanced packaging development times is multi-physics simulation.

In this talk, a high level overview of the different AI applications will be presented along with some key challenges for advanced packaging. Some of the commonly used advanced packaging solutions will be discussed, and the corresponding challenges/tradeoffs will be presented, spanning power, thermal, manufacturing and reliability. The use of multi-physics simulations to address these challenges, with some examples and use cases will be presented. Lastly, the use of AI itself to enhance those multi-physics simulations will also be discussed. 

By the end of this talk, the attendee will be able to make the connections between the high level needs posed by AI applications, the challenges that advanced packaging needs to address, and how multi-physics simulations can help address those challenges effectively. The attendee will be able to identify some of the tradeoffs that need to be made, to deliver AI at the scale, volume and complexity needed currently and over the next several years.

The fast-paced evolution of technology, driven by innovations such as 5G, artificial intelligence, augmented reality and quantum computing, has fueled a growing demand for high-performance integrated circuits (ICs). This demand requires integrated circuits (ICs) to operate at higher speeds and with reduced power consumption. Transistor scaling consistently followed Moore’s Law for decades, but in the recent years, we have witnessed a slowdown as we achieve the physical limits of manufacturing silicon transistors. In spite of these obstacles, the process technology still managed to keep up, but the steady increase in transistor density has resulted in escalating lithography costs and complexities, leading to significant yield losses that hurt the product. To mitigate these challenges and achieve optimal performance, power, area, and cost (PPAC), design technology co-optimization (DTCO) and system technology co-optimization (STCO) initiatives have been adopted. However, despite advancements in PPAC optimization, the continuous scaling of transistors, coupled with the growing complexity of logic design, lower power consumption and increasingly complex 3D IC package schemes, introduces new obstacles for failure analysis. Current and future package technologies incorporate multiple layers of various components stacked on top of one another with decreasing bump pitch, projected to reach sub-micron dimensions. This complex package design makes it difficult to inspect and access specific components or interconnects of interest while keeping the device still intact.

This presentation will delve into the Failure Analysis challenges highlighted by a comprehensive study conducted by over 50 experts from more than 30 leading organizations across industry, academia, national labs, and research institutes, facilitated by the Electron Devices Failure Analysis Society (EDFAS) through its Technology Roadmap initiative. As chair of the Die Level Isolation Roadmap committee, I will present the key Electrical Fault Isolation (EFI) challenges, identify critical gaps, and outline indicators for success. This covers five critical areas of focus: (1) laser-based, photon emission, and thermal techniques; (2) 2D/2.5D/3D packaging; (3) product yield, test, and diagnostics; (4) leading edge technologies; and (5) system level, analog/RF, and digital functional analysis. Furthermore, this presentation will highlight the key challenges associated with post-isolation and physical failure analysis, encompassing sample preparation, nano-probing/scanning probe microscopy, Scanning Electron Microscopy (SEM), and Focused Ion Beam (FIB) microscopy. Furthermore, this presentation will provide a brief overview of key package-level failure analysis (FA) bottlenecks. Finally, it will explore opportunities for collaboration between the simulation community and failure analysis experts to improve the quality and success of failure analysis.

Signify is the world leader in conventional and in LED (connected) lighting systems, software and
services. The past decades, in-house engineering reliability models were built to predict the field
performance of products. Validation of former models always turned out cumbersome because
of availability of trustful field failure data. However, the advantage of having abundant products
in the field can be outbalanced by difficulties in getting proper feedback on field failures. Even
though in some specific cases, failures are recorded properly, it remains hard to estimate the FITs
(failures in time), due to the lack of a precise assessment of the operational burning hours.

Signify’s installed base of connected light points is currently exceeding 100 Mpcs and is further
expanding. Consequently, it offers solid ground for executing big data analytics. The requested
data yields from the outdoor luminaire controllers on the lighting poles that are exchanging
various information via a gateway to the cloud. Detailed information on failed and operational
products can be retrieved from this cloud data. We used it to validate more accurately the
forecasts from the in-house reliability calculators. This presentation debates the challenges of
cleaning the datasets of connected outdoor lighting systems for these purposes.

These specific challenges result from the lighting products’ specifics (business & product),
compared to e.g. those of cars or industrial equipment. We will explain these differences, discuss
some of the resulting challenges and show how those were tackled to yield relevant reliability
information from the available cloud data.

The global thermal management market, valued at over USD 12.6 billion in 2022, is projected to reach approximately USD 32.83 billion by 2032, growing at a compound annual growth rate (CAGR) of 10.10% from 2023 to 2032. The increasing need for thermal management is driven by several factors, including the rising thermal requirements in 5G communication devices, the growing demand for effective heat management solutions in the consumer electronics sector, the necessity for thermal management to ensure the safety and durability of electric vehicles (EVs), the increasing demand for carbon dioxide reduction and fuel-efficient thermal systems, and advancements in thermal interface materials. However, the field faces new challenges such as the complexity of geometry and physics as devices become more powerful, necessitating virtual prototyping for efficient cooling. Traditional design and manufacturing techniques are reaching their performance limits, prompting the need for innovative approaches and workflows. Additionally, the extended design space requires more computational resources and accessible components and models. Sustainability is also a key concern, with smart thermal management enhancing energy efficiency and minimizing environmental impact to achieve both a comfortable environment and efficient energy consumption. Hexagon’s thermal simulation solutions play a crucial role in early detection and resolution of temperature-driven reliability and performance issues, thereby enhancing product quality during the design phase. This presentation highlights two key simulation technologies:
BCI ROM: A Reduced Order Model (ROM) technology for ultra-fast thermal analysis, essential for EV development. It enables the creation of highly accurate and lightweight thermal ROMs for components such as inverters, batteries, and motors, facilitating fast temperature prediction for transient heat losses.
Solder Joint Defects: A Multiphysics Approach: This approach addresses prevalent defects in the assembly of Ball Grid Array (BGA), Chip Scale Package (CSP), or Package on Package (PoP) components onto Printed Circuit Boards (PCBs). By simulating thermal expansion and the dynamic movement of solder fluid, this research provides critical insights into the mechanical integrity of solder joints, paving the way for enhancements in electronic packaging reliability.

To advance the design of SiC power MOSFETs, we’ve developed a data-driven modeling procedure using experimental characterization and machine learning (ML)-based optimization. This approach, integrating ANSYS optiSLang and Synopsys TCAD, allows us to carefully examine the inherent design trade-offs between on-state resistance and short-circuit robustness for 1.2kV planar SiC MOSFETs.