As electronic systems grow in complexity and development cycles shorten, reliability can no longer be treated as a downstream validation activity. The most critical reliability decisions are made early, often before testing even begins.​

This plenary talk explores the shift from reliability testing to reliability thinking. It shows how simulation, co-design, and structured failure learning can be combined to influence early design choices, reduce late-stage surprises, and enable more robust products. Rather than focusing on specific methods, the presentation offers a strategic perspective on how reliability becomes a design driver through integration, mindset, and organizational alignment.

Since the announcement of TSMC’s CoPoS (chip on panel on substrate) in 2025, the glass packaging has been getting lots of traction for high-end and high-performance applications. Today, the package of choice of HPC (high-performance computing) driven by AI (artificial intelligence) is the CoWoS (chip on wafer on substrate). The TSV (through-silicon via) interposer of CoWoS is fabricated on a silicon wafer. However, because of the area efficiency (lower cost), the TSV-interposer is replaced by the TGV (through-glass via) interposer (CoPoS) which is fabricated on a glass panel. CoPoS is scheduled to be shipped in Q1 of 2029. In this lecture, a brief fundamental of glass packaging will be presented. Also, the reliability of flip chips on glass substrates with microbump and Cu-Cu hybrid bonding interconnects will be discussed. Some recommendations will be provided.

Flexible and hybrid electronics (FHE) combine additively printed electronics on bendable, flexible or highly stretchable substrates with the performance of thinned silicon-based semiconductors to enable applications that include wearable medical devices and industrial sensors.  Many of these applications require thin, soft, conformal, or stretchable attributes for “wearability” in human healthcare or integration on industrial or infrastructure systems that must survive extreme conditions.  Some applications require the electronics and interconnects to be printed “in-place” on existing surfaces and components.

This presentation will review the design and fabrication challenges associated with interfacing hard and soft electronic components, the use of sustainable materials, particle-free inks, advances in printing and processing methods, and testing of FHE systems.  Applications that will be featured include the use of highly stretchable conductors, fluid transport, printed electrochemical and robotic sensors, RF devices, power conversion, and efforts to enable use at extreme conditions that include high temperature, power and current operation will be described.

The increasing demand of modern society for energy, and the quest for more sustainable technologies drives innovations in today’s power electronics towards more efficient and green power conversion. Power semiconductors as key components of power converter switching cells play an important role for keeping up the pace with the emerging requirements. Namely, moving from silicon (Si) to wide-band gap (WBG) power semiconductor technology has enabled more advanced power converter designs and a shift to new paradigms in power electronics. Today, Silicon Carbide (SiC) is the preferred WBG semiconductor material for various applications such as electrical vehicles (EV) powertrains and charging infrastructure, solar inverters, uninterruptible power supplies in datacenters, industrial power supplies and motor drives.  SiC power MOSFETs represent a switch solution with higher blocking voltage and lower switching losses in comparison to their Si-counterparts. However, the same electrical performance and reliability levels cannot be achieved by simply replacing Si with SiC power devices in the standard packages. High system performance utilizing SiC power devices strongly relies on enhanced package design considering thermal, electrical, and reliability aspects. Higher integration together with a complex multi-parameter design space calls for multi-physics modeling of SiC power modules and discrete packages. Here, more accurate multi-physics modeling provides the basis for trustful virtual prototyping, supporting design development leading to cost-optimized hardware prototypes and more accurate estimation of actual power losses, necessary to achieve high-efficiency/high-power-density converters. This plenary talk will put the requirements for more accurate modelling of SiC power semiconductor discrete and module packages into perspective, illustrating the ongoing shift in industry from Si to SiC power semiconductor technology.

The increasing demand for highly integrated, miniaturized, and multifunctional microsystems in sensing, actuation, and communication technologies is driving continuous innovation in micro- and nanoelectromechanical systems (MEMS/NEMS). As device dimensions shrink and operating frequencies increase, the performance, reliability, and long-term stability of MEMS/NEMS are increasingly governed by tightly coupled mechanical, electrical, thermal, and surface-related phenomena. Accurate prediction of such behavior therefore requires advanced multiphysics models capable of capturing interactions across multiple length and time scales.

However, the predictive power of these models critically depends on rigorous experimental validation at the nanoscale. In this context, advanced nanometrology based on atomic force microscopy (AFM) has emerged as a key enabler for quantitative validation of multiphysics models in MEMS/NEMS. AFM-based techniques provide unique access to local mechanical properties, surface forces, electromechanical coupling, thermal transport, and dissipation mechanisms with nanometer spatial resolution and high force sensitivity. Variants such as conductive AFM, Kelvin probe force microscopy, piezoresponse force microscopy, and other AFM-based techniques enable direct probing of parameters that are otherwise inaccessible by conventional metrology.

This keynote talk will put the requirements for accurate multiphysics modeling of MEMS/NEMS devices into perspective, emphasizing the role of AFM-based nanometrology for model validation and refinement. By highlighting representative case studies, the talk will illustrate how quantitative AFM measurements can bridge the gap between simulations and real device behavior, enabling trustful virtual prototyping, improved design robustness, and more reliable performance prediction in next-generation MEMS/NEMS technologies.

This keynote explores Artificial Intelligence (AI)-enabled reliability prediction and prognostics and health management (PHM) for semiconductor packaging and heterogeneous integration. Key challenges are analyzed through the pillars of data, models, and compute. Major bottlenecks include the scarcity of standardized and reliable datasets, the scaling of the current AI-based predictive models with very limited variables and parameters, and the need for GPU acceleration in semiconductor packaging reliability field. It concludes with future directions for AI-enabled reliability prediction and PHM in electronic systems.

AI infrastructure is entering a power-density inflection where sustained utilization is gated as much by packaging, thermo-mechanical interfaces, and facility energy constraints as by compute. Over the next five years, heterogeneous integration (chiplets, 2.5D/3D integration, and high-bandwidth memory) will shift system bottlenecks into power delivery networks, memory and data movement, and the stability of thermal interfaces under realistic warpage, clamp loads, and mission-profile cycling. In parallel, inference demand is expanding toward hybrid and edge deployments, increasing the number of operating modes and the importance of deployable, serviceable reference designs. This paper synthesizes current industry trajectories and a thermo-mechanical architecture view to provide a practical roadmap for silicon suppliers and hyperscalers. It highlights (i) integration rules as a new competitive moat, (ii) hardware-software co-design and observability as an operations flywheel, (iii) memory bandwidth as a dominant system tax, (iv) thermo-mechanical enablement as the limiter for multi-kW packages, and (v) energy and water strategy as first-order design constraints. We propose actionable roadmaps, validation