Program of courses

Instructor(s) : Pradeep Lall, Auburn University

Prognostics Health Management (PHM) is the interrogation of system state and the assessment of product survivability in deployed systems using non-destructive assessment of underlying damage. System health is generally assessed in the actual operating environment. The prior stress history to which the system may have been subjected may not be known in several cases. Prognostics health management is very different from reliability prediction which often assumes pristine materials and uses models which require definitive specification of environmental loads.

In recent past, PHM has emerged as a key enabling technology to provide an early warning of failure. Early warning may be used to forecast planned-maintenance and assess the potential for life extensions. PHM has been applied to machines, aircraft, bridges, electronics, and bio-implantable systems. Avionic systems require ultra-high reliability operation with minimal downtime. Automotive safety features such as anti-lock braking, airbags, and collision avoidance systems depend on electronics for their performance and reliability. Implantable biological systems are ften life-sustaining in nature. Deployed electronic systems often may be subjected to multiple thermal environments. Thermal environments may change due to operational environments or change in usage profiles. Decision-support for re-deployment requires PHM based methods for assessment of the operational readiness of electronic systems based on accrued damage and residual life in intended environment. PHM will enable self-cognizant systems capable of assessing their own real-time performance under actual usage conditions and adaptively trigger risk-mitigation actions to virtually eliminate unplanned failures.

Topics covered include

• Approaches for monitoring system health
• Methods for data analysis
• Leading indicators of failure for various types of failure mechanisms
• Algorithms for data reduction and parameter extraction
• Approaches for residual life estimation
• Statistical assessment of uncertainty of system survivability in future deployment

The course is intended to introduce the students to PHM solutions for electronic systems using early indicators of failure for scheduled maintenance and assessment of system survivability of a deployed system. Specifically the students will have the knowledge needed to:

• Identify solutions for health monitoring of products and systems
• Use leading indicators-of-failure for various electronic failure mechanisms
• Develop algorithms and models for data reduction and parameter extraction
• Implement methods for assessment of accrued damage
• Use statistical techniques for assessment of uncertainty

BIOGRAPHY

Pradeep Lall is the Thomas Walter Professor in the Department of Mechanical Engineering with a joint appointment in Department of Finance. He is the Director of NSF Center for Advanced Vehicle and Extreme Environment Electronics at Auburn University. He is author and co-author of 2-books, 11 book chapters, and over 225 journal and conference papers in the field of electronic packaging with emphasis on design, modeling and predictive techniques. Dr. Lall is a Fellow of the ASME. He is recipient of the Samuel Ginn College of Engineering Senior Faculty Research Award and Three-Motorola Outstanding Innovation Awards. He is an Associate Editor for the ASME Journal of Electronic Packaging, IEEE Transactions on Components and Packaging Technologies, and IEEE Transactions on Electronics Packaging Manufacturing.

EFFICIENT BOARD-LEVEL RELIABILITY TESTING OF LEAD-FREE ELECTRONICS – FOCUSED ON DROP, VIBRATION AND THERMOMECHANICAL LOADINGS

Reliability of electronic devices has become an important success factor in the highly competitive global electronics markets. This is mostly because increasing heat dissipation, current densities and mechanical loadings of power components have made electrical interconnections more vulnerable to failures. On the other hand, new materials and technologies are continuously introduced into the novel devices. For these reasons more extensive and comprehensive reliability testing of new products has become ever more important. However, longer testing time adds the cost of new products not only due to the direct expenses related to testing but also due to increased time-to-market of new products. Therefore, efficient reliability testing of electronic devices is the main topic of this short course.

In order to assess the reliability of electrical devices one needs to know i) how the loadings are generated in operational environments and how do they correlate with the accelerated test conditions, ii) how the materials respond to different types of loadings, and iii) how the evolution of solder interconnection microstructures (e.g. the growth of IMC layers, defect formation and recrystallization) being generated by thermal, electrical and mechanical loadings affect the failure modes and mechanisms. In addition, the reliability of electrical devices under drop and vibration loadings is greatly dependent on their loading histories, because the microstructures of solder interconnections are not stable but evolve continuously.

This course will benefit those who are interested in gaining a general understanding of the reliability of lead-free electronics as well as those who are interested in the state of the art of failure physics of electrical interconnections experiencing mechanical shocks or vibrations. They include researchers, design engineers, manufacturing engineers, quality assurance and materials personnel as well as the management implementing manufacturing strategies.

Topics covered are:

• General reliability aspects of electrical devices
• Commonly used materials in soldering of SMT electronics and their characteristics (component metallizations, PWB surface finishes and lead-free solders)
• Reliability testing
  • Thermal cycling and power cycling tests
  • Drop testing (JESD22-B111) and vibration testing
  • Numerical methods: significance testing and the Weibull analysis
  • Methods of failure analysis
• Failure modes and mechanisms under the test conditions
  • Thermal cycling tests: microstructural evolution in lead-free solder interconnections and the role of recrystallization
  • Drop and vibration tests: reliability improvement by modifications of intermetallic layers and solder compositions
  • Essential similarities and differences between the failure modes and mechanisms under drop, vibration and thermal cycling test
• Potential alternatives for comprehensive and cost efficient reliability testing
  • Combined load tests: effects of temperature on the drop/vibration reliability
  • Concurrent load tests
  • Optimization of thermal cycling test parameters

Dr. Toni Mattila is a research scientist and a docent at the Helsinki University of Technology, Department of Electronics. He received the D.Sc. (Tech.) degree in electrical engineering and the M.Sc. degree in materials science and engineering from the Helsinki University of Technology. Since 1996, he has been working with electronics production and reliability of electronic devices both in industrial and academic setting. Before joining HUT in 1999 he worked in Tellabs and Nokia. His research has focused on electronics production technologies, soldering in electronics, failure modes and mechanisms of electronic assemblies, and the development of improved methods for reliability testing and lifetime prediction. He is also a frequent reviewer in several scientific journals and an active member of the IEEE-CPMT society.

“Complete, true-electromagnetic power integrity analysis of integrated circuits through high levels of abstraction, continuum models, and physics-based simulation”

Outline

Scaling of transistors and integrated circuits has brought about decades of wonders in electronics. As this progression in integration continues, with minimum dimensions smaller than 10,000th of the width of a human hair, or below 100 nano meters, electrical power consumed by integrated circuits and systems is seen to become a significant challenge and a critical design constraint, referred to as the “Power Wall”. This workshop introduces the reader, both intuitively and theoretically, to the rise of this challenge to electronic integration. More importantly, it highlights a less known challenge, that of power integrity, or the quality of the power supply within integrated circuits, bringing to plain view key relationships between scaling, power integrity, and energy. Revealing key aspects impacting power integrity, such as resistance, inductance, and capacitance, the workshop discusses numerous modeling and analysis methods employed to study integrated circuit power integrity, developed by researchers in the academia as well as the industry. The significance of on-chip inductance to power integrity and physical design optimization is discussed. Concepts of differential power distribution, and continuum modeling, that overcome limitations of traditional design and analysis, are explored. Integrated circuit physical design enhanced by power integrity awareness is discussed.

Two aspects in particular are novel about this course. We explore the application of continuum modeling of layers of an integrated circuit relevant to power integrity through high levels of abstraction, and analyze PI through physics-based simulation conducted by a finite-difference method. Through such abstraction, continuum-based modeling, and physics-based simulation, we demonstrate the feasibility of early, front-end analysis of an integrated circuit and system for power integrity. Such front-end analysis permits pre-layout optimization of the physical design of integrated circuits, saving chip area, metal resource usage, overall design effort, and through minimization of noise, chip energy consumption.

This workshop is the first, focused attempt to explore the emerging significance of power integrity to integrated circuits, packages, boards, and systems of the present and the future. The course will benefit architects and designers seeking a general understanding of power integrity and its significance to integrated circuit design and optimization. It will be of particular benefit to system designers seeking to optimize energy consumption, and electronic design automation engineers as well as design managers engaged in nanoscale chip design. Simulation tool developers will find the application of continuum modeling and simulation to IC floorplanning and physical design of much interest.

Course software: RLCSim.EXE accessible at: http://www.anasim.com/category/software/

Topics list:

• Fundamentals of Power, Power integrity, IC’s, and Scaling
• Power integrity (PI) in circuit and system design
• The “Power Integrity Wall”
• IC Floorplanning, and constraints
• PI modeling and analysis in IC’s today, and limitations
• Abstraction and Continuum Modeling of IC’s for PI
• Front-end, system-level integrated circuit PI analysis
• PI-aware IC floorplanning, optimization, and chip-package co-design
• Front-end co-simulation (PI/EMI)

Instructor bio:

Raj Nair has 22+ years of engineering and research experience in the industry and academia and holds over 40 patents in VLSI and general electronics. He has conducted extensive investigations into power deliver and integrity management at the electronic system, circuits, and device levels in his efforts, which includes work at Intel® Corporation, where he researched and conceived of integrated CMOS voltage regulation for microprocessor power integrity management. Raj founded ComLSI Inc. and Anasim Corp., where he worked on developing advanced, patented techniques and tools for ULSI power integrity analysis and management. He is the author of a book “Power Integrity Analysis and Management for Integrated Circuits” to be published by Prentice-Hall in Spring 2010.

COURSE RAFFLE PRIZES (number of prizes to be determined) Book “Power Integrity Analysis and Management for Integrated Circuits” by Raj Nair & Donald Bennett.

Course Title:

Trends of Power Electronic Packaging (4 hours)

Instructors:

Dr. Yong Liu Fairchild Semiconductor Corp., South Portland, Maine, USA

Instructors’ Bio

Dr. Yong Liu has been with Fairchild Semiconductor Corp in South Portland, Maine since 2001 as a Senior Member Technical Staff from 2008, and a Member Technical Staff from 2004 to 2007, and a Principal Engineer from 2001 to 2004. He is now a Fairchild global team leader of electrical, thermal-mechanical modeling and analysis. His main interest area is IC packaging, modeling and simulation, reliability and material characterization. In last a few years he and his team have been working on advanced IC package modeling and simulation, which include the pioneering work on assembly manufacture process and the electromigration induced failures for chip scale wafer level packages. He has been invited to give keynotes talks and presentations at international conferences Eurosime, ICEPT, EPTC and universities in US, Europe and China. He has co-authored over 100 papers in journals and conferences and has filed over 40 US patents in the area of 3D/Stack/TSV IC packaging and power devices. Dr. Liu obtained his BS, Master and Ph.D degrees in Nanjing Univeristy of Science and Technology in 1983, 1987 and 1990 respectively. He once was promoted in a breaking rule as a full professor at Zhejiang University of Technology. Dr. Liu was awarded Alexander von Humboldt Fellowship and studied as a Humboldt fellow at Tech University of Braunschweig, Germany in 1994. In 1997, he was awarded Alexander von Humboldt European Fellowship and studied as a Humboldt European fellow at University of Cambridge, England. In 1998, he worked as a post-doctor at Semiconductor Focus Center and Computational Mechanics Center, Rensselaer Polytechnic Institute (RPI). In 2000, he worked as a staff opto package engineer at Nortel Networks at Boston. Since he joined Fairchild in 2001, he was awarded the first Fairchild President Award in 2008, Fairchild Key Technologist in 2006, Fairchild BIQ award in product innovation in 2005, and Fairchild award for power of pen first place in 2004. Yong Liu is currently an IEEE Senior member and has been actively in technical committees of IEEE ECTC, EuroSime, EPTC and ICEPT.

Course Scope:

Power electronic packaging is one of the fastest growing segments and wide applications in the power electronic industry due to the rapid advances in power integrated circuit (IC) fabrication and the demands of a growing market in almost all areas of power electronic application such as portable electronics, consumer electronics, home electronics, computing electronics, automotive, railway and high/strong power industry. However, due to the intrinsic structural nature, the requirement for power product is extremely high, especially in thermal and electrical environment. The design rule and development of power packaging in material and structure layout are quite different from regular IC packaging. The development of power packages depends on the development of power device integration and the co-design automation simulation tool. Current power devices have two major integration modes: Monolithic integration and hybrid integration. Monolithic integration includes power integrated circuits, high voltage integrated circuits (HVIC), and intelligent discrete power devices, combined with functional integration and the integration of passive elements. Hybrid integration includes the standard power module and the intelligent power module (IPM).

This course will present a state-of-art and in-depth overview of recent advances in power electronic packaging design and modeling. A review of recent advances in power electronic packaging is presented based on the development of power device integration. The short course will cover in more detail how advances in both semiconductor content and power advanced package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, the role of modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.

Course Objectives

• Provide an overview of power electronic technologies including both the design and modeling trends.
• Fundamental understanding of the power packaging evolution and development trends in monolithic integration and hybrid integration.
• Understanding the development of the power SIP/3D/stack/TSV and power module packaging technology.
• Understanding of challenges and failure modes of power electronic packaging Understanding of the overall modeling and simulation in power packaging development, importance of the co-design automation and how the modeling/simulation will help the power electronic packaging.

Outline

1.Introduction

2.Challenges of power packaging

• a.Impact of power die shrinkage
• b.Power SOC vs SIP
• c.Power package foot print pitch vs PCB pad pitch
• d.New materials for power die e.New materials for power package

3.Challenges of power packaging modeling

• a.Modeling tool and limits
• b.Modeling theories and limits
• c.Modeling methodologies and recent progress
• d.Multiple physics modeling

4.Trends in Discrete Power MOSFET Package

• a.The trends of using epoxy molding compound
• b.Trends of current carrying capability
• c.Low Rds(on) and multiple direction heat transfer
• d.Trends of power VDMOSFET WL-CSP

5.Trends in Power IC packaging

• a.Higher power density at the die level
• b.Smaller package footprints
• c.Inthgration solution (SoC for IC and LDMOSFET) for low power application

6.Trends in Power SIP/3D/Stack packaging

• a.Side by side placement power SIP - Lower power buck converter - Hybrid high power module including automotive module
• b.Stack die power SIP including multiple phase buck
• c.Stack power active and passive chips
• d.Wafer level power stack package with TSV
• e.Stack power module
• f.Overview the current most new power packaging

7. Power Package Electrical Isolation Design

• a. Design rule for isolation
• b. Creepage and clearance
• c. Required function to estimate creepage distance
• d. Categories of application and standards
• f. Geometry design layout consideration

8. Thermal Management, Design and Cooling for Power Electronics

• a. Heat transfer from Junction to System
• b. Thermal analysis and design
• c. Power components and PCB Boards
• d. Cooling Device
  • Air flow cooling
  • Liquid cooling
  • Micro channel cooling
• f. Thermal measurements

9. Trends in power packaging modeling

• a.Modeling role in power electronic industry
• b.Co-design simulation automation platform
• c.Advanced modeling methodologies for challenges
• d.Thermal management design and modeling
• e.Power packaging passivation cracking and method
• f.Power packaging electromigration simulation
• g.Power packaging assembly and testing simulation

10. Summary

Who should attend:

The course is designed for staff members, technical managers, design and manufacturing personnel, and reliability engineers in microelectronic and power electronics companies. Although the course covers most recent advances in this area, the course does not assume prior knowledge of these issues and hence is of interest for both experts and new actors in this area. It is also good for universities professors, staff and students for further study and discussion.

Packaging of High Brightness LED for Solid State Lighting

Course Scope and Objectives:

Light emitting diode (LED) is a semiconductor device based on the effect of electroluminescence. Due to the limitation in efficacy and the lack of white light, LED was not suitable for general lighting applications in the past. With the advancement of semiconductor materials and packaging technologies, the illumination performance of LED has been greatly improved. Ten years ago high power (one watt) white LEDs were introduced with efficiencies high enough to kick off serious discussion on using LEDs for solid state lighting (SSL) applications. Over the last decade the performance of high brightness LED (HB-LED) has continued to increase from about 20 Lumens/Watt to over 100 Lumens/Watt today. There is no longer any doubt about the feasibility of LEDs for SSL. The remaining question is when LEDs will dominate all lighting markets. SSL has major advantages such as energy saving, environmental friendliness, and long operational life. LED Packaging is the major enabling technology to achieve these merits. This short course will review the technology trends of lighting sources and introduce the features of LED. Technical issues in packaging LED components such as interconnection, phosphor deposition, and encapsulation will be elaborated in detail. Considerations in thermal and power management will be evaluated. Efforts will also be made to investigate optical design, analysis and characterization. Applications of HB-LED for general SSL and special lighting will be highlighted. Furthermore, technology roadmap and IP issues will be discussed.

Course Outline:

• Review of electroluminescence and lighting technology trends
• Overview of packaging structures of LED
• Interconnection and vertical LED
• Phosphor deposition for color tuning
• Encapsulation materials and processes
• Considerations in thermal management
• Optical design, analysis and characterization
• HB-LED arrays for general solid state lighting
• HB-LED modules for special lighting applications
• Driving circuit and intelligent control design
• Reliability engineering of HB-LED packaging
• LED measurement and standards
• Technology roadmap and patent mapping

Who Should Attend

This short course is intended for scientists in research institutions, faculty members and postgraduate students in universities, professional engineers and technical managers in the industries who are involved or interested in the design, materials, processing, and assembly of high brightness LED for solid state lighting.

Lecturer Biography:

Ricky Lee received his PhD degree from Purdue University. Currently he is Professor of Mechanical Engineering and Director of Center for Advanced Microsystems Packaging (CAMP) at the Hong Kong University of Science & Technology (HKUST). His research activities cover flip chip technologies and wafer level packaging, through silicon vias and 3D packaging, LED and optoelectronics packaging, lead-free soldering and solder joint reliability. Ricky has substantial publications in international journals/conference proceedings and received several best paper awards. He also co-authored three books and owns three technical patents. Ricky is Fellow of IEEE and ASME, and Institute of Physics (UK). In addition, he is elected IEEE CPMT Distinguished Lecturer and receives CPMT Electronics Manufacturing Technology Award. Furthermore, he serves as Editor-in-Chief of IEEE Transactions on Components & Packaging Technologies and Associate Editor of IEEE Transactions on Advanced Packaging. Ricky is the project leader to implement HB-LED SSL on Hong Kong subway trains.

Sheng Liu is a Changjiang scholar professor of Mechanical Engineering at Huazhong University of Science and Technology and he has a dual appointment at Wuhan National Laboratory for Optoelectronics. He once was a tenured faculty at Wayne State University. He has over 17 years experience in LED/MEMS/IC packaging. He has extensive experience in consulting with many leading multinational and Chinese companies. He once won prestigious White House/NSF Presidential Faculty Fellow Award in 1995, ASME Young Engineer Award in 1996, NSFC Overseas Young Scientist Award in 1999 in China, IEEE CPMT Exceptional Technical Achievement Award in 2009, and Chinese Electronic Manufacturing and Packaging Technology Society Special Achievement Award in 2009. He has been an associate editor of IEEE Transaction on Electronic Packaging Manufacturing since 1999 and an associate editor of Journal of Frontiers of Optoelectronics in China since 2007. He is currently one of 11 National Committee Members in LED under Ministry of Science and Technology of China from 2006-2011. He obtained his Ph.D. from Stanford University in 1992. He is ASME Fellow. He has filed and owed more than 80 patents in China and USA, and has published more than 300 technical articles, edited more than 9 proceedings in English for ASME and IEEE, he has co-authored the first book in LED packaging for lighting applications, which will appear at the end of 2009.

Course Scope and Objectives:

In todays rapidly changing business environment, the electronics industry is facing numerous innovation and design challenges requiring the introduction of novel materials, increasingly complex device design with nanoscale precision and faster and more reliable testing procedures. Besides traditional multi-physics finite-element based approaches multiscale modeling and molecular modeling have found an growing number of applications, such as in investigating delamination processes in electronic packaging or in controlling intermetallics creation and growth at interfaces.
This course provides an overview of atomistic simulations as they are being used in todays industrial R&D environment to assess mechanical, thermal and electrical properties of bulk materials, defects, and heterogeneous interfaces.
Using application examples taken from MD's R&D portfolio, the capabilities and limitations of electronic structure methods and forcefield based approaches are discussed and brought into perspective of industrial requirements for materials property prediction, accuracy of results and long term predictability.
Application examples include the calculation of elastic moduli, the modeling of grain boundaries and the effect of impurities on their strength, the modeling of metal/dielectric semiconductor/dielectric interfaces, the prediction of thermal expansion coefficients and the prediction of diffusion coefficients. The description of surface adsorption and reactions as related to CVD , PVD, and ALD processes will constitute another class of examples. Finally, an outlook will be presented on the atomic-scale modeling of thermal conductivity in nanoscale structures.

Course Outline:

1. Overview of atomic-scale modeling and simulation techniques
2. Computation of materials properties
   • Structure of solids, surfaces, and interfaces
   • Elastic moduli
   • Interfaces and cohesion
   • Heat capacity
   • Thermal expansion
   • Diffusion
   • Surface reactivity
   • Electronic, optical and magnetic properties
3. Polymers and fluids
   • 3.1.Polymer properties
   • 3.2.Fluids
4. Future trends

Who Should Attend

The ½ day course addresses engineers, scientists and technical managers in the electronics industry who are faced with materials issues and who would like to learn about methods to gain deeper understanding of materials and processes relevant to the industry.

Lecturer Biography

Erich Wimmer:
Before becoming one of the founders of Materials Design, Erich was director of contract research at Molecular Simulations, Inc. and founder of an industrial consortium for electronic, optical, and magnetic materials. Between 1985 and 1992, he was Technical Director at Cray Research where he promoted the application of large-scale supercomputer simulations for solving industrial problems in chemistry and materials science. Erich initiated and led an industrial consortium of companies such as DuPont, Exxon and 3M to develop a new generation of software ("UniChem"). Prior to joining Cray Research, he held a faculty position in physical chemistry at the University of Vienna, Austria. Erich is author and co-author of over 100 scientific publications and book contributions. A noted authority in computational materials science, he has lectured in the U.S., Europe, Japan, and Korea, and organized several international conferences. Erich is co-founder and one of the editors of the Journal of Computer-Aided Materials Design. He also serves as referee of international journals including Science and Physical Review, and was recently nominated “Outstanding Referee” by the American Physical Society. He is also a long-time member of the American Chemical Society and the Materials Research Society.
He received his Ph.D. in chemistry in 1977 from the University of Technology in Vienna, Austria. As research associate in the group of Prof. A. J. Freeman at Northwestern University, Erich was instrumental in the development of a highly accurate quantum mechanical method. Known as the FLAPW method, it calculates structural, electronic and chemical properties of solids and surfaces.

Alexander Mavromaras:
Alexander Mavromaras is head of worldwide customer support at Materials Design Inc. and responsible for sales in Europe and South Africa. Before joining Materials Design in 2000, Alexander worked as a software developer at the Fraunhofer Institute for Computer Graphics Research, Darmstadt, as a postdoctoral candidate at the Institut de Chimie de la Matière Condensée in Bordeaux and at the Institut Supérieur des Matériaux et Mécaniques Avancés in Le Mans, France.
He received his PhD in theoretical physics with focus on electronic structure code development from Darmstadt University in 1998. During his time as a PhD student and postdoctoral candidate, Alexander pursued a number of international collaborations with universities in Sweden and France. Alexander teaches specialized courses on computational materials modeling at the Institute Supérieure des Matériaux et Mécaniques Avancés, Le Mans, France.